In development of a semiconductor device, particularly a semiconductor storage device, ever finer patterning is developed for memory cells to achieve larger capacities and lower costs. In a semiconductor storage device mounted with a floating gate structure such as a NAND flash memory device, the wire pitch between word lines to be a control gate in a gate portion is made ever finer. Such finer patterning of LSIs is actively promoted to achieve performance improvement such as a faster operation and lower power consumption of elements due to higher integration and the reduction in manufacturing costs. In recent years, flash memories in minimum processing dimensions of, for example, 20 nm or so have been in mass production and still finer patterning and increasing technical difficulty are expected in the future. To realize a high-quality, high-performance, and low-cost semiconductor device in the face of rapid development of ever finer patterning, it is necessary to further reduce the parasitic capacitance between gate structures. In a next-generation flash memory device, both the cell width and the width between cells are extremely narrow due to still finer patterning and a technology to provide a cavity region is under development, instead of embedding a dielectric film between gate structures in a memory cell region, to inhibit electric interference between cells. By intentionally forming a cavity instead of the dielectric film embedded between gate structures in the memory cell region, a parasitic capacitance generated between gate structures can be reduced so that performance of a memory device can be improved.
However, if a cavity is formed between gate structures, mechanical strength of the gate structure is extremely weakened and with the development of ever finer patterning of devices, a problem of cracks in the dielectric film deposited in the memory cell region and a problem of a toppling gate structure in the memory cell portion are caused.